NXP Semiconductors MWCT101 S Series, Reference Manual

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Table 37-4. WCT101xS register implementation (continued)
Register/Offset WCT1014S WCT1015S WCT1016S
aRA - aRP / 188 - 1C4
SC1Q - SC1X /148 - 164
RQ - RX / 1C8 - 1E4
Reserved/Not
implemented Available/Implemented Available/Implemented
SC1Y - SC1AF / 168 -
184
RY - RAF / 1E8 - 204
Reserved/Not
Implemented Reserved/Not Implemented Available/Implemented
37.3 DMA Support on ADC
Applications may require continuous sampling of the ADC (4K samples/sec) that may
have considerable load on the CPU. Though using the Programmable Delay Block (PDB)
to trigger the ADC may reduce some CPU load, the ADC supports DMA request
functionality for higher performance when the ADC is sampled at a very high rate or in
cases where the PDB is bypassed. The ADC can trigger the DMA (via DMA request)
upon conversion completion.
For most cases, the DMA request can be directly triggered from ADC conversion
completion. The device also supports another way to trigger DMA: via the TRGMUX.
The TRGMUX will provide user a more flexible DMA triggering scheme using software
based on different application requirements, for example, the DMA can be triggered after
multiple ADC conversion completion instead of every ADC conversion completion.
37.4 ADC Hardware Interleaved Channels
On devices with two ADCs, there are several special ADC channels which support
hardware interleave between multiple ADCs. Taking ADC0_SE4 and ADC1_SE14
channels as an example, these two channels can work independently, but they can also be
hardware interleaved as following diagram. In the hardware interleaved mode, a signal on
the pin PTB0 can be sampled by both ADC0 and ADC1. The interleaved mode is enabled
by SIM_CHIPCTL[ADC_INTERLEAVE_EN] bits.
The hardware interleave implementation on this device is as following:
• ADC0_SE4 and ADC1_SE14 channels are interleaved on PTB0 pin
• ADC0_SE5 and ADC1_SE15 channels are interleaved on PTB1 pin
• ADC1_SE8 and ADC0_SE8 channels are interleaved on PTB13 pin
• ADC1_SE9 and ADC0_SE9 channels are interleaved on PTB14 pin
Chapter 37 ADC Configuration
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 973