NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 320 / 1761

16.4.5.11.4 Fields
Field Function
7
NOP
No Op enable
0b - Normal operation
1b - No operation, ignore the other bits in this register
6
SAST
Set All START Bits (activates all channels)
0b - Set only the TCDn_CSR[START] bit specified in the SSRT field
1b - Set all bits in TCDn_CSR[START]
5-4
—
Reserved
3-0
SSRT
Set START Bit
Sets the corresponding bit in TCDn_CSR[START]
16.4.5.12 Clear Error Register (CERR)
16.4.5.12.1 Offset
Register Offset
CERR 1Eh
16.4.5.12.2 Function
The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR
to disable the error condition flag for a given channel. The given value on a register write
causes the corresponding bit in the ERR to be cleared. Setting the CAEI bit provides a
global clear function, forcing the ERR contents to be cleared, clearing all channel error
indicators. If the NOP bit is set, the command is ignored. This allows you to write
multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
16.4.5.12.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
0 0 0
W
NOP CAEI
0
CER R
Reset 0 0 0 0 0 0 0 0
Memory map/register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
320 NXP Semiconductors