NXP Semiconductors MWCT101 S Series, Reference Manual

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0
1
SPI Slave
MISO
SCK input
delayed LPSPISCK
LPSPI_CFGR1[SAMPLE]
LPSPI_SCK
LPSPI_SIN
LPSPI Master
Figure 45-7. Clock Loopback
See the device datasheet for the specific input setup time in master loopback mode.
45.4.3 Slave Mode
LPSPI slave mode:
• uses the same shift register and logic that master mode uses
• does not use the Clock Configuration Register (CCR)
• during SPI bus transfers, requires that the Transmit Command Register (TCR)
remain static (unchanging)
45.4.3.1 Transmit and Command FIFO commands
Before enabling the LPSPI in slave mode, the Transmit Command Register (TCR) should
be initialized, although the Transmit Command Register register will not update until
after the LPSPI is enabled. After being enabled, the Transmit Command Register should
only be changed if the LPSPI is idle. In slave mode, the LPSPI command word in the
Transmit Command Register (TCR) controls SPI attributes (using bits and fields in
registers). Before the LPSPI_PCS input asserts, the transmit FIFO must be filled with
transmit data, or the transmit error flag will set.
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1404 NXP Semiconductors