NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 890 / 1761

33.7.2.3 Suspend-Abort Mechanism
Any low priority AHB access can be suspended by a high priority AHB master request.
The ongoing transaction is suspended at 64 bit boundary. The suspended transaction is
restarted after the high priority master is served and the high priority transaction
including data prefetch is completed. While a transaction is in suspended state, it may be
aborted if a transaction by the same suspended master is made to a location which is
different from the location of the suspended transaction.
Any ongoing transaction is aborted if a request from the same master arrives for a
location other than the location at which the transaction is going on. The abort can
happen at any point of time.
33.7.2.4 HBURST Support
QuadSPI controller supports HBURST and HSIZE on the AHB interface. HBURST
indicates if the transfer forms part of a burst. Four, eight and sixteen beat bursts are
supported and the burst may be either incrementing or wrapping. HSIZE indicates the
size of the transfer. 8, 16, 32 and 64 bit data size are supported. In case of WRAP
accesses, QuadSPI generates aligned accesses to Serial Flash if there is no buffer hit for
any incoming non-sequential AHB access. In case there is a buffer hit, the incoming
address in the haddr line is latched as it is. If the total burst size is more than the data
prefetch size an error response is generated and QSPI_FR[AIBSEF] is set. The data
perfetch size can be defined by QSPI_BUFxCR[ADATSZ] or data size mentioned in the
sequence pointed to by the SEQID field when ADATSZ is programmed as zero. A few
examples are shown in the figure below:
Functional Description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
890 NXP Semiconductors