NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1094 / 1761

In this diagram, only one PDB channel n, and one Pulse-Out y are shown. The PDB-
enabled control logic and the sequence error interrupt logic are not shown.
40.2.5 Modes of operation
PDB ADC trigger operates in the following modes:
• Disabled—Counter is off, all pre-trigger and trigger outputs are low if PDB is not in
back-to-back operation of Bypass mode.
• Debug—Counter is paused when processor is in Debug mode.
• Enabled One-Shot—Counter is enabled and restarted at count zero upon receiving a
positive edge on the selected trigger input source or software trigger is selected and
SC[SWTRIG] is written with 1. In each PDB channel, an enabled pre-trigger asserts
once per trigger input event. The trigger output asserts whenever any of the pre-
triggers is asserted.
• Enabled Continuous—Counter is enabled and restarted at count zero. The counter is
rolled over to zero again when the count reaches the value specified in the modulus
register, and the counting is restarted. This enables a continuous stream of pre-
triggers/trigger outputs as a result of a single trigger input event.
• Enabled Bypassed—The pre-trigger and trigger outputs assert immediately after a
positive edge on the selected trigger input source or software trigger is selected and
SC[SWTRIG] is written with 1, that is the delay registers are bypassed. It is possible
to bypass any one or more of the delay registers; therefore, this mode can be used in
conjunction with One-Shot or Continuous mode.
40.3 Memory map and register definition
PDB memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4003_1000 Status and Control register (PDB1_SC) 32 R/W 0000_0000h 40.3.1/1098
4003_1004 Modulus register (PDB1_MOD) 32 R/W 0000_FFFFh 40.3.2/1101
4003_1008 Counter register (PDB1_CNT) 32 R 0000_0000h 40.3.3/1101
4003_100C Interrupt Delay register (PDB1_IDLY) 32 R/W 0000_FFFFh 40.3.4/1102
4003_1010 Channel n Control register 1 (PDB1_CH0C1) 32 R/W 0000_0000h 40.3.5/1102
4003_1014 Channel n Status register (PDB1_CH0S) 32 R/W 0000_0000h 40.3.6/1103
4003_1018 Channel n Delay 0 register (PDB1_CH0DLY0) 32 R/W 0000_0000h 40.3.7/1104
4003_101C Channel n Delay 1 register (PDB1_CH0DLY1) 32 R/W 0000_0000h 40.3.8/1105
Table continues on the next page...
Memory map and register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1094 NXP Semiconductors