NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1446 / 1761

46.3.1.23.4 Fields
Field Function
31-19
—
Reserved
18-16
ADDRCFG
Address Configuration
Configures the condition that will cause an address to match.
000b - Address match 0 (7-bit)
001b - Address match 0 (10-bit)
010b - Address match 0 (7-bit) or Address match 1 (7-bit)
011b - Address match 0 (10-bit) or Address match 1 (10-bit)
100b - Address match 0 (7-bit) or Address match 1 (10-bit)
101b - Address match 0 (10-bit) or Address match 1 (7-bit)
110b - From Address match 0 (7-bit) to Address match 1 (7-bit)
111b - From Address match 0 (10-bit) to Address match 1 (10-bit)
15-14
—
Reserved
13
HSMEN
High Speed Mode Enable
Enables detection of the High-Speed Mode master code of slave address 0000_1XX, but does not cause
an address match on this code. When set and any HS-mode master code is detected, the FILTEN and
ACKSTALL bits are ignored until the next STOP condition is detected.
0b - Disables detection of HS-mode master code
1b - Enables detection of HS-mode master code
12
IGNACK
Ignore NACK
When Ignore NACK is set, the LPI2C slave will continue transfers after a NACK is detected. Ignore NACK
bit is required to be set in Ultra-Fast Mode.
0b - Slave will end transfer when NACK is detected
1b - Slave will not end transfer when NACK detected
11
RXCFG
Receive Data Configuration
0b - Reading the Receive Data register will return received data and clear the Receive Data flag
(MSR[RDF]).
1b - Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return
the Address Status register and clear the Address Valid flag. Reading the Receive Data register
when the Address Valid flag is clear, will return received data and clear the Receive Data flag
(MSR[RDF]).
10
TXCFG
Transmit Flag Configuration
The transmit data flag will always assert before a NACK is detected at the end of a slave-transmit
transfer. This can cause an extra word to be written to the transmit data FIFO.
• When TXCFG=0, the Transmit Data register is automatically emptied when a slave-transmit
transfer is detected. This causes the transmit data flag to assert whenever a slave-transmit transfer
is detected, and causes the transmit data flag to negate at the end of the slave-transmit transfer.
• When TXCFG=1, the Transmit Data flag will assert whenver the Transmit Data register is empty,
and the Transmit Data flag will negate when the Transmit Data register is full. This allows the
Transmit Data register to be filled before a slave-transmit transfer is detected, but can cause the
Transmit Data register to be written before a NACK is detected on the last byte of a slave transmit
transfer.
0b - Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data
register is empty
1b - Transmit Data Flag will assert whenever the Transmit Data register is empty
9 SMBus Alert Enable
Table continues on the next page...
Memory Map and Registers
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1446 NXP Semiconductors