NXP Semiconductors MWCT101 S Series, Reference Manual

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• there is a falling edge at phase B signal and phase A signal is at logic zero;
• there is a falling edge at phase A signal and phase B signal is at logic one;
and the FTM counter decrement happens when:
• there is a falling edge at phase A signal and phase B signal is at logic zero;
• there is a falling edge at phase B signal and phase A signal is at logic one;
• there is a rising edge at phase B signal and phase A signal is at logic zero;
• there is a rising edge at phase A signal and phase B signal is at logic one.
phase A
phase B
FTM counter
increment/decrement
FTM counter
MOD
CNTIN
0x0000
Time
+1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1
-1
-1
-1
Figure 41-104. Quadrature Decoder – Phase A and Phase B Encoding Mode
The following figure shows the FTM counter overflow in up counting. In this case, when
the FTM counter changes from MOD to CNTIN, TOF and TOFDIR bits are set. TOF bit
indicates the FTM counter overflow occurred. TOFDIR indicates the counting was up
when the FTM counter overflow occurred.
Functional Description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1268 NXP Semiconductors