NXP Semiconductors MWCT101 S Series, Reference Manual

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Table 33-2. QuadSPI_MCR[SCLKCFG] bit field description
(continued)
Bit field name Bit field description
1: Selecting BUS_CLK as AHB read interface clock and module clock. Mandatory for HSRUN 112
configuration.
SCLKCFG[5] HyperRAM selection for Flash B - Reference clock selection for DQS for Flash-B
0: Clock from SCLKCFG [3] selected as DQS ( HyperRAM Disabled)
1: External RWDS from Flash B selected as DQS ( HyperRAM Enabled)
NOTE: When HyperRAM is enabled , the 2 x Internal reference clock clock is also required by
QuadSPI apart from sfif clock as HyperRAM is a DDR protocol. If user has configured
PLAT_CLK at 80 MHz then the PCC divider for Quadspi asynchronous clock selection
must be programmed to divby2 and SCLKCFG[5] must be programmed to 1 for
HyperRAM functional operation.
SCLKCFG[4] Internal reference clock (async clock domain) source selection for Quadspi
0: PLL_DIV1 is clock source of Quadspi Internal reference Clock
1: FIRC_DIV1 is clock source of Quadspi Internal reference Clock
SCLKCFG[3]
Reference clock selection for DQS for Flash-B
0: Inverted Clock from SCLKCFG [2] selected as DQS
1: Clock from SCLKCFG [2] selected as DQS
SCLKCFG[2] Reference clock selection for DQS for Flash-B
0: Internal Reference Clock selected as DQS
1: Loopback clock from PAD SCKB selected as DQS
SCLKCFG[1]
Reference clock selection for DQS for Flash-A
0: Inverted Clock from SCLKCFG [0] selected as DQS
1: Clock from SCLKCFG [0] selected as DQS
SCLKCFG[0] Reference clock selection for DQS for Flash-A
0: Internal Reference Clock selected as DQS
1: Loopback clock from PAD SCKA selected as DQS
33.1.11 QuadSPI_SOCCR[SOCCFG] implementation
Table 33-3. QuadSPI_SOCCR[SOCCFG] bit field
description
Bit field name Bit field description
SOCCFG[7:0]
SOC configuration: Fine delay chain configuration for Flash A
7F: Delay of 127 buffers and 128 muxes
7E :Delay of 126 buffers and 127 muxes
7D :Delay of 125 buffers and 126 muxes
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-
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Table continues on the next page...
Chapter 33 Quad Serial Peripheral Interface (QuadSPI)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 823