NXP Semiconductors MWCT101 S Series, Reference Manual

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SRAM_L
SRAM_U
Code bus
System bus
Frontdoor
Backdoor Slave Port
Code Cache
Controller
SRAM Controller
M1 Master Port (CSM)
M0 Master Port (CCM)
Tag Arrays
Cache
Data Arrays
Cache
LMEM
Figure 29-2. LMEM Interface to SRAM
29.4.2.2 SRAM Arrays
The on-chip SRAM is split into two logical arrays, SRAM_L and SRAM_U.
SRAM_L size is 128 KBytes.
SRAM_U size is 128 KBytes.
Valid address ranges for SRAM_L and SRAM_U are then defined as:
• SRAM_L = (0x20000_0000 - 128 KBytes) to 0x1fff_ffff
• SRAM_U = 0x2000_0000 to (0x200 128 KBytes)
SRAML_SIZE and SRAMU_SIZE do not have to be equal.
29.4.2.3 SRAM Accesses
The SRAM is split into two logical arrays that are 32-bits wide:
• SRAM_L — Accessible by the code bus of the core and by the backdoor port.
• SRAM_U — Accessible by the system bus of the core and by the backdoor port.
The backdoor port makes the SRAM accessible to the non-core bus masters (such as
DMA).
Functional Description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
650 NXP Semiconductors