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Table 49-11. Message buffer code for Tx buffers
CODE Description
Tx Code BEFORE tx
frame
MB RTR
Tx Code AFTER
successful
transmission
Comment
and then the code will
automatically return to
RANSWER (0b1010).
The CPU can also write
this code with the same
effect. The remote
response frame can be
either a data frame or
another remote request
frame depending on the
RTR bit value. See
and
details.
SRR — Substitute Remote Request
Fixed recessive bit, used only in extended format. It must be set to one by the user for
transmission (Tx Buffers) and will be stored with the value received on the CAN bus for
Rx receiving buffers. It can be received as either recessive or dominant. If FlexCAN
receives this bit as dominant, then it is interpreted as an arbitration loss.
1 = Recessive value is compulsory for transmission in extended format frames
0 = Dominant is not a valid value for transmission in extended format frames
IDE — ID Extended Bit
This field identifies whether the frame format is standard or extended.
1 = Frame format is extended
0 = Frame format is standard
RTR — Remote Transmission Request
This bit affects the behavior of remote frames and is part of the reception filter. See
, and the description of the RRS field in Control 2 register (CTRL2)
for additional details.
If FlexCAN transmits this bit as '1' (recessive) and receives it as '0' (dominant), it is
interpreted as an arbitration loss. If this bit is transmitted as '0' (dominant), then if it is
received as '1' (recessive), the FlexCAN module treats it as a bit error. If the value
received matches the value transmitted, it is considered a successful bit transmission.
Chapter 49 FlexCAN
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors
1649
Summary of Contents for MWCT101 S Series
Page 2: ...MWCT101xS Series Reference Manual Rev 3 07 2019 2 NXP Semiconductors...
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Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
Page 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...
Page 284: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 284 NXP Semiconductors...
Page 430: ...Functional Description MWCT101xS Series Reference Manual Rev 3 07 2019 430 NXP Semiconductors...
Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
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Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
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Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
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