NXP Semiconductors MWCT101 S Series, Reference Manual

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• Each pair of channels can be combined to generate a PWM signal with independent
control of both edges of PWM signal
• The FTM channels can operate as pairs with equal outputs, pairs with
complementary outputs, or independent channels with independent outputs
• The deadtime insertion is available for each complementary pair
• Generation of match triggers
• Software control of PWM outputs
• Up to 4 fault inputs for global fault control
• The polarity of each channel is configurable
• The generation of an interrupt per channel
• The generation of an interrupt when the counter overflows
• The generation of an interrupt when the fault condition is detected
• The generation of an interrupt when a register reload point occurs
• Synchronized loading of write buffered FTM registers
• Half cycle and Full cycle register reload capacity
• Write protection for critical registers
• Backwards compatible with TPM
• Testing of input capture mode
• Direct access to input pin states
• Dual edge capture for pulse and period width measurement
• Quadrature decoder with input filters, relative position counting, and interrupt on
position count or capture of position count on external event
• The FTM channels can be selected to generate a trigger pulse on channel output
instead of a PWM
• Dithering capability to simulate fine edge control for both PWM period or PWM
duty cycle
Introduction
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1128 NXP Semiconductors