NXP Semiconductors MWCT101 S Series, Reference Manual

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4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1
channel (n) output
FTM counter
accumulator
0x1E
0x01
overflow
0x04
3 2
channels (n) and (n+1) are in
Combine Mode with high-true pulses
and Complementary
channel (n) ELSB:ELSA = 2'b10
CNTIN = 0x0000
MOD = 0x0006
C(n)V = 0x0002
channel (n) FRACVAL = 0x03
C(n+1)V = 0x0004
channel (n+1) FRACVAL = 0x00
T is the period of one unit of FTM counter
3 2 1
Combine duty cycle DC1 =
(C(n)V - C(n+1)V) x T =
0x0002 x T
4 5 6 0 1 2 3 4 5 6 0 1 2 3
dithering
(one unit of
FTM counter)
0x07 0x0A
channel (n+1) output
0x0D 0x10
Combine duty cycle DC2 =
(C(n)V - C(n+1)V - 0x0001) x T =
0x0001 x T
Combine duty cycle DC1 =
(C(n)V - C(n+1)V) x T =
0x0002 x T
Combine duty cycle DC1 =
(C(n)V - C(n+1)V) x T =
0x0002 x T
Combine duty cycle DC1 =
(C(n)V - C(n+1)V) x T =
0x0002 x T
Combine duty cycle DC1 =
(C(n)V - C(n+1)V) x T =
0x0002 x T
Figure 41-123. Channel (n) Match Edge Dithering in Combine Mode
The channel (n+1) match edge dithering is enabled when a non-zero value is written to
the channel (n+1) FRACVAL.
For the channel (n+1) match edge dithering, the channel (n+1) has an internal 5-bit
accumulator. At the end of each PWM period, the channel (n+1) FRACVAL value is
added to the channel (n+1) accumulator. When this accumulator overflows (that is, the
result of the adding is greater or equal than 0x20), the accumulator remains with the rest
of the subtraction: (the result of this adding - 0x20).
If there was not the overflow of the channel (n+1) accumulator in the current PWM
period, the channel (n+1) match edge is not modified, that is, it happens on channel (n+1)
match. However, if there was the overflow of the channel (n+1) accumulator, the channel
(n+1) match edge happens when (FTM counter = C(n+1)V + 0x0001).
The following figure shows an example of the channel (n+1) match edge dithering when
the channels (n) and (n+1) are in Combine mode.
4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1
channel (n) output
FTM counter
accumulator
0x1E 0x01
overflow
0x04
3 2
channels (n) and (n+1) are in
Combine Mode with high-true pulses
and Complementary
channel (n) ELSB:ELSA = 2'b10
CNTIN = 0x0000
MOD = 0x0006
C(n)V = 0x0002
channel (n) FRACVAL = 0x00
C(n+1)V = 0x0004
channel (n+1) FRACVAL = 0x03
T is the period of one unit of FTM counter
3 2
1
Combine duty cycle DC1 =
(C(n)V - C(n+1)V) x T =
0x0002 x T
4 5 6 0 1 2 3 4 5 6 0 1 2 3
dithering
(one unit of
FTM counter)
0x07 0x0A
channel (n+1) output
0x0D 0x10
Combine duty cycle DC2 =
(C(n)V - C(n+1)V + 0x0001) x T =
0x0003 x T
Combine duty cycle DC1 =
(C(n)V - C(n+1)V) x T =
0x0002 x T
Combine duty cycle DC1 =
(C(n)V - C(n+1)V) x T =
0x0002 x T
Combine duty cycle DC1 =
(C(n)V - C(n+1)V) x T =
0x0002 x T
Combine duty cycle DC1 =
(C(n)V - C(n+1)V) x T =
0x0002 x T
Figure 41-124. Channel (n+1) Match Edge Dithering in Combine Mode
Functional Description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1286 NXP Semiconductors