NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1591 / 1761

• If RXERRCNT increases to a value greater than 127, it is not incremented further,
even if more errors are detected when being a receiver. At the next successful
message reception, the counter is set to a value between 119 and 127 to return to
Error Active state.
• TXERRCNT_FAST and RXERRCNT_FAST error counter values increment and
decrement based on errors detected only in the data phase of CAN FD frames with
the BRS bit set, following the same increment and decrement rules as TXERRCNT
and RXERRCNT counters. These counters do not wrap around and get stuck at their
maximum value (255). They stop counting and keep their values frozen when
FlexCAN is in Bus Off state. They are reset when FlexCAN leaves Bus Off state and
restart counting after FlexCAN returns to Error Active state.
• When FlexCAN is in Pretended Networking mode, RXERRCNT and
RXERRCNT_FAST keep counting errors and error flags are stored. TXERRCNT
and TXERRCNT_FAST preserve their values and do not change, because no
transmission occurs under Pretended Networking mode. Error counters and error
flags that changed values when in Pretended Networking mode are updated in ECR
and ESR1 when FlexCAN returns to Normal mode. The FAST error flags in ESR1
register will not be set if FlexCAN is in Pretended Networking mode.
NOTE
See Fault confinement in the CAN Protocol standard (ISO
11898-1) for details.
49.4.2.8.3 Diagram
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R RXERRCNT_FAST TXERRCNT_FAST
W 0 0
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
RXERRCNT TXERRCNT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
49.4.2.8.4 Fields
Field Function
31-24
RXERRCNT_FA
ST
Receive Error Counter for fast bits
Table continues on the next page...
Chapter 49 FlexCAN
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1591