NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1198 / 1761

Table 41-5. Channel Modes Selection (continued)
DECAPEN MCOMBINE COMBINE CPWMS MSB:MSA ELSB:ELSA Mode Configuratio
n
clear on
channel (n+1)
match)
X1 Low-true
pulses (clear
on channel (n)
match, and
set on
channel (n+1)
match)
1 0 0 0 X0 See Table
41-6 .
Dual Edge
Capture
One-Shot
Capture mode
X1 Continuous
Capture mode
Table 41-6. Dual Edge Capture Mode — Edge Polarity Selection
ELSB ELSA Channel Port Enable Detected Edges
0 0 Disabled No edge
0 1 Enabled Rising edge
1 0 Enabled Falling edge
1 1 Enabled Rising and falling edges
41.5.5 Input Capture Mode
The Input Capture mode is selected when:
• DECAPEN = 0
• MCOMBINE = 0
• COMBINE = 0
• CPWMS = 0
• MSB:MSA = 0:0, and
• ELSB:ELSA ≠ 0:0
When a selected edge occurs on the channel input, the current value of the FTM counter
is captured into the CnV register, at the same time the CHF bit is set and the channel
interrupt is generated if enabled by CHIE = 1. See the following figure.
When a channel is configured for input capture, the FTMxCHn pin is an edge-sensitive
input. ELSB:ELSA bits determine which edge, falling or rising, triggers input-capture
event.
Functional Description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1198 NXP Semiconductors