NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1392 / 1761

45.3.1.15.2 Function
Writes to either the Transmit Command Register or Transmit Data Register will push the
data into the transmit FIFO, in the order that the data are written. The Command Register
should only be written using 32-bit writes. Command Register writes will be tagged and
cause the command register to update, after that entry reaches the top of the FIFO. This
allows changes to the command word and the transmit data itself to be interleaved.
Changing the command word will cause all subsequent SPI bus transfers to be performed
using the new command word.
• In master mode, writing a new command word does not initiate a new transfer,
unless TXMSK is set. Transfers are initiated by transmit data in the transmit FIFO, or
by a new command word (with TXMSK set). Hardware will clear TXMSK when the
LPSPI_PCS negates.
• In master mode, if the command word is changed before an existing frame has
completed, then the existing frame will terminate and the command word will then
update. The command word can be changed during a continuous transfer, if CONTC
of the new command word is set and the command word is written on a frame size
boundary.
• In slave mode, the command word should be changed only when the LPSPI is idle
and there is no SPI bus transfer.
Avoid register reading problems: Reading the Transmit Command Register will return
the current state of the command register. Reading the Transmit Command Register at the
same time that the Transmit Command Register is loaded from the transmit FIFO, can
return an incorrect Transmit Command Register value. It is recommended:
• to either read the Transmit Command Register when the transmit FIFO is empty,
• or to read the Transmit Command Register more than once and then compare the
returned values.
45.3.1.15.3 Diagram
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
CPOL CPHA
PRESCAL E
Reserved
PC S
LSB F
BYS W
CONT
CONTC
RXMSK TXMSK
WIDTH
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved FRAMESZ
W
Reset
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
Memory Map and Registers
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1392 NXP Semiconductors