NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1304 / 1761

42.4.1.4 Module Control Register (MCR)
42.4.1.4.1 Offset
Register Offset
MCR 8h
42.4.1.4.2 Diagram
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DBG_E N
DOZE_EN
SW_RS T
M_CEN
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
42.4.1.4.3 Fields
Field Function
31-4
—
This read-only field is reserved and always has the value 0
3
DBG_EN
Debug Enable Bit
Stops the timer channels when the device enters Debug mode
0b - Stop timer channels in Debug mode
1b - Allow timer channels to continue to run in Debug mode
2
DOZE_EN
DOZE Mode Enable Bit
Stops the timer channels when the device enters DOZE mode
0b - Stop timer channels in DOZE mode
1b - Allow timer channels to continue to run in DOZE mode
1
SW_RST
Software Reset Bit
Resets all channels and registers, except the Module Control Register. The Software Reset bit remains
set until cleared by software.
NOTE: Before clearing the Software Reset bit, software must wait for 4 peripheral clocks (for clock
synchronization and reset propagation).
0b - Timer channels and registers are not reset
1b - Reset timer channels and registers
0 Module Clock Enable
Memory Map and Registers
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1304 NXP Semiconductors