NXP Semiconductors MWCT101 S Series, Reference Manual

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If the timer stop bit is enabled, the timer counter will continue decrementing until the
next rising edge of the shift clock is detected, at which point it will finish. Although the
timer output is forced low during the stop bit, the timer shift clock can toggle during the
stop bit, but does not generate shift events.
A timer enable condition can be detected in the same cycle as a timer disable condition (if
timer stop bit is disabled), or on the first rising edge of the shift clock after the disable
condition (if stop bit is enabled). Receive shift registers with stop bit enabled will store
the contents of the shift register into the shift buffer and verify the state of the input data
on the configured shift edge while the timer is in the stop state condition. If there is no
configured edge between the timer disable and the next rising edge of the shift clock then
the final store and verify do not occur.
48.4.4 Pin operation
The pin configuration for each timer and shifter can be configured to use any FlexIO pin
with either polarity. Each timer and shifter can be configured as an input, output data,
output enable or bidirectional output. A pin configured for output enable can be used as
an open drain (with inverted polarity, since the output enable assertion would cause logic
zero to be output on the pin) or to control the enable on the bidirectional output. Any
timer or shifter could be configured to control the output enable for a pin where the
bidirectional output data is driven by another timer or shifter.
48.4.4.1 Pin Synchronization
When configuring a pin as an input (this includes a timer trigger configured as a pin
input), the input signal is first synchronized to the FlexIO clock before the signal is used
by a timer or shifter. This introduces a small latency of between 0.5 to 1.5 FlexIO clock
cycles when using an external pin input to generate an output or control a shifter. This
sets the maximum setup time at 1.5 FlexIO clock cycles.
If an input is used by more than one timer or shifter then the synchronization occurs once
to ensure any edge is seen on the same cycle by all timers and shifters using that input.
Note that FlexIO pins are also connected internally, configuring a FlexIO shifter or timer
to output data on an unused pin will make an internal connection that allows other
shifters and timer to use this pin as an input. This allows a shifter output to be used to
trigger a timer or a timer output to be shifted into a shifter. This path is also synchronized
to the FlexIO clock and therefore incurs a 1 cycle latency.
So when using a Pin input as a Timer Trigger, Timer Clock or Shifter Data Input, the
following synchronization delays occur:
Chapter 48 Flexible I/O (FlexIO)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1549