NXP Semiconductors MWCT101 S Series, Reference Manual

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QUADSPI
Clock Gen
Sampling
Serial Flash
Clock
Data
Out
SCK - Serial Flash Clock
SI_IO[0:7] - Serial Flash Data
1
5
2
4
3
Figure 33-8. Serial Flash Sampling Clock Overview
The rising edge of the internal reference clock is taken as timing reference for the data
output of the serial flash. After a time of t
Del,total
the data arrives at the internal sampling
stage of the QuadSPI module. According to the Serial Flash Sampling Clock Overview
figure, the following parts of the delay chain contribute to t
Del,total
:
1. Output delay of the serial flash clock output of the device containing the QuadSPI
module
2. Wire delay of application/PCB from the device containing the QuadSPI module to
the external serial flash device
3. Clock to data out delay of the external serial flash device, including input and output
delays
4. Wire delay of application/PCB from the external serial flash device to the device
containing the QuadSPI module
5. Device delay corresponding to the input data
NOTE
The amount of total delay t
Del,total
is specific to the
characteristics of the actual implementation. Also, the serial
flash device clock (SCK) is inverted with respect to the
QuadSPI internal reference clock.
33.12.2 Supported read modes
Some modes listed here may not be available on this chip. See the chip-specific QuadSPI
information for the read modes that this chip supports.
Sampling of Serial Flash Input Data
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
922 NXP Semiconductors