NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1307 / 1761

Field Function
0b - Timer has not timed out
1b - Timeout has occurred (timer has timed out)
42.4.1.6 Module Interrupt Enable Register (MIER)
42.4.1.6.1 Offset
Register Offset
MIER 10h
42.4.1.6.2 Diagram
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TIE3 TIE2 TIE1 TIE0 W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
42.4.1.6.3 Fields
Field Function
31-4
—
This read-only field is reserved and always has the value 0
3
TIE3
Channel 3 Timer Interrupt Enable
Enables interrupt generation when:
• the Channel 3 Timer Interrupt Enable bit (TIE3) is set to 1
• and if the corresponding Timer Interrupt Flag (MSR[TIF3]) is asserted (=1, timeout has occurred)
0b - Disabled
1b - Enabled
2
TIE2
Channel 2 Timer Interrupt Enable
Enables interrupt generation when:
• the Channel 2 Timer Interrupt Enable bit (TIE2) is set to 1
• and if the corresponding Timer Interrupt Flag (MSR[TIF2]) is asserted (=1, timeout has occurred)
Table continues on the next page...
Chapter 42 Low Power Interrupt Timer (LPIT)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1307