NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1365 / 1761

Write accesses to a locked register are ignored and do not generate a bus error.
44.4.7 Interrupt
The RTC interrupt is asserted whenever a status flag and the corresponding interrupt
enable bit are both set. It is always asserted on POR, and software reset. The RTC
interrupt is enabled at the chip level by enabling the chip-specific RTC clock gate control
bit. The RTC interrupt can be used to wakeup the chip from any low-power mode.
The RTC seconds interrupt is an edge-sensitive interrupt with a dedicated interrupt vector
that is generated once a second and requires no software overhead (there is no
corresponding status flag to clear). It is enabled in the RTC by the time seconds interrupt
enable bit and enabled at the chip level by setting the chip-specific RTC clock gate
control bit. The frequency of the seconds interrupt defaults to 1 Hz, but can instead be
configured to trigger every 2, 4, 8, 16, 32, 64 or 128 Hz.
Chapter 44 Real Time Clock (RTC)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1365