51.5.4.3 SAMPLE instruction
The SAMPLE instruction obtains a sample of the system data and control signals present
at the MCU input pins, and just before the boundary scan register cells at the output pins.
This sampling occurs on the rising edge of TCK in the Capture-DR state when the
SAMPLE instruction is active. The sampled data is viewed by shifting it through the
boundary scan register to the TDO output during the Shift-DR state. There is no defined
action in the Update-DR state. Both the data capture and the shift operation are
transparent to system operation.
51.5.4.4 EXTEST external test instruction
EXTEST selects the boundary scan register as the shift path between TDI and TDO. It
allows testing of off-chip circuitry and board-level interconnections by driving preloaded
data contained in the boundary scan register onto the system output pins. Typically, the
preloaded data is loaded into the boundary scan register using the SAMPLE/PRELOAD
instruction before the selection of EXTEST. EXTEST asserts the internal system reset for
the MCU to force a predictable internal state when performing external boundary scan
operations.
51.5.4.5 ENABLE_SOC_DATA1 instruction
The ENABLE_SOC_DATA1 instruction captures SoC data and selects the SOC_DATA
register for connection as the shift path between TDI and TDO.
51.5.4.6 HIGHZ instruction
HIGHZ selects the bypass register as the shift path between TDI and TDO. When
HIGHZ is active all output drivers are placed in an inactive drive state (for example, high
impedance). HIGHZ also asserts the internal system reset for the MCU to force a
predictable internal state.
51.5.4.7 CLAMP instruction
CLAMP allows the state of signals driven from MCU pins to be determined from the
boundary scan register when the bypass register is selected as the serial path between TDI
and TDO. CLAMP enhances test efficiency by reducing the overall shift path to a single
Functional description
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Summary of Contents for MWCT101 S Series
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Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
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Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
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Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
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Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
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