NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1143 / 1761

41.4.3.8.1 Offset
Register Offset
STATUS 50h
41.4.3.8.2 Function
The STATUS register contains a copy of the status flag CHF bit in CnSC for each FTM
channel for software convenience.
Each CHF bit in STATUS is a mirror of CHF bit in CnSC. All CHF bits can be checked
using only one read of STATUS. All CHF bits can be cleared by reading STATUS
followed by writing 0x00 to STATUS.
Hardware sets the individual channel flags when an event occurs on the channel. CHF is
cleared by reading STATUS while CHF is set and then writing a 0 to the CHF bit.
Writing a 1 to CHF has no effect.
If another event occurs between the read and write operations, the write operation has no
effect; therefore, CHF remains set indicating an event has occurred. In this case, a CHF
interrupt request is not lost due to the clearing sequence for a previous CHF.
41.4.3.8.3 Diagram
Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CH7F CH6F CH5F CH4F CH3F CH2F CH1F CH0F
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
41.4.3.8.4 Fields
Field Function
31-8
—
Reserved
7-0 Channel n Flag
Chapter 41 FlexTimer Module (FTM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1143