NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 637 / 1761

LMEM
Core System Master (CSM) bus
Processor System (PS) bus
Cache data arrays
Cache I&D code bus
Code cache
controller
Core Code Master (CCM) bus
Processor Code (PC) bus
Cache tag arrays
Cr
ossbar s
witch
P
rocessor
Backdoor port
SRAM lower
SRAM upper
LMEM
controller
Figure 29-1. Local memory controller block diagram
NOTE
The SRAM and cache controllers reside within the LMEM, but
the single-port synchronous RAM arrays used by these
controllers are external.
The LMEM contains address decode logic for the PC and PS buses. This logic routes the
core's accesses to the various system resources. The address spaces are device-specific.
See the chip-specific LMEM information for the address space decode details.
29.2.2 Cache features
A cache is a block of high-speed memory locations containing address information
(commonly known as a tag) and the associated data. The purpose is to decrease the
average time of a memory access. Caches operate on two principles of locality:
• Spatial locality — An access to one location is likely to be followed by accesses
from adjacent locations (for example, sequential instruction execution or usage of a
data structure).
• Temporal locality — An access to an area of memory is likely to be repeated within a
short time period (for example, execution of a code loop).
Chapter 29 Local Memory Controller (LMEM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 637