Field
Function
FAULTEN1
Enables the fault control in channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0b - The fault control in this pair of channels is disabled.
1b - The fault control in this pair of channels is enabled.
13
SYNCEN1
Synchronization Enable For n = 2
Enables PWM synchronization of registers C(n)V and C(n+1)V.
0b - The PWM synchronization in this pair of channels is disabled.
1b - The PWM synchronization in this pair of channels is enabled.
12
DTEN1
Deadtime Enable For n = 2
Enables the deadtime insertion in the channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0b - The deadtime insertion in this pair of channels is disabled.
1b - The deadtime insertion in this pair of channels is enabled.
11
DECAP1
Dual Edge Capture Mode Captures For n = 2
Enables the capture of the FTM counter value according to the channel (n) input event and the
configuration of the dual edge capture bits.
This field applies only when DECAPEN = 1.
DECAP bit is cleared automatically by hardware if Dual Edge Capture – One-Shot mode is selected and
when the capture of channel (n+1) event is made.
0b - The dual edge captures are inactive.
1b - The dual edge captures are active.
10
DECAPEN1
Dual Edge Capture Mode Enable For n = 2
Enables the Dual Edge Capture mode in the channels (n) and (n+1). See
.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
9
COMP1
Complement Of Channel (n) For n = 2
In Complementary mode the channel (n+1) output is the inverse of the channel (n) output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0b - If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the
channel (n+1) output is the same as the channel (n) output. If the channel (n+1) is in Output
Compare Mode, EPWM or CPWM, the channel (n+1) output is independent from channel (n)
output.
1b - The channel (n+1) output is the complement of the channel (n) output.
8
COMBINE1
Combine Channels For n = 2
Used on the selection of the combine mode for channels (n) and (n+1). See
.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
7
MCOMBINE0
Modified Combine Mode For n = 0
Used on the selection of the modified combine mode for channels (n) and (n+1). See
.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
6
FAULTEN0
Fault Control Enable For n = 0
Enables the fault control in channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0b - The fault control in this pair of channels is disabled.
1b - The fault control in this pair of channels is enabled.
Table continues on the next page...
Chapter 41 FlexTimer Module (FTM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors
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Summary of Contents for MWCT101 S Series
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Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
Page 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...
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Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
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Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
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Page 1514: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 1514 NXP Semiconductors...
Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
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