NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 534 / 1761

SCG_VERID field descriptions
Field Description
VERSION SCG Version Number
26.3.2 Parameter Register (SCG_PARAM)
Note: Writing to this register will result in a transfer error.
Address: 4006_4000h base + 4h offset = 4006_4004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DIVPRES 0 0 CLKPRES
W
Reset
* * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * * * * * *
* Notes:
DIVPRES field: The reset value is controlled by which SCG System Dividers are used by Soc. •
CLKPRES field: The reset value is controlled by which SCG Clock Sources are used by Soc. Please reference the
Reference manual clocking chapter.
•
SCG_PARAM field descriptions
Field Description
31–27
DIVPRES
Divider Present
Indicates which system clock dividers are present in this instance of SCG.
DIVPRES[27]=1 System DIVSLOW is present.
DIVPRES[28]=1 System DIVBUS is present
DIVPRES[31]=1 System DIVCORE is present
26–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
CLKPRES Clock Present
Indicates which clock sources are present in this instance of SCG. Any bits not defined in this bit field are
Reserved and always has the value 0 when read.
CLKPRES[0] Reserved
CLKPRES[1]=1System OSC (SOSC) is present
CLKPRES[2]=1Slow IRC (SIRC) is present
CLKPRES[3]=1Fast IRC (FIRC) is present
CLKPRES[6]=1System PLL (SPLL) is present
Memory Map/Register Definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
534 NXP Semiconductors