NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 530 / 1761

26.1.2 Oscillator and SPLL guidelines
If PLL is used, then oscillator needs to be in high range only, SCG_SOSCCFG[RANGE]
on 11 as used in reference clock before disabling SOSC:
If the current system clock is SOSC, then following should be taken care by software:
• Configure all reset sources to be 'Interrupt' (not as 'Reset') via RCM_SRIE
• The SOSC should be disabled via SCG_SOSCCSR[SOSCEN]
• After disabling SOSC, configure the reset source back to reset via RCM_SRIE
• When SPLL is enabled, both LOC and LOL must be configured as reset only
(SOSCCSR[SOSCCMRE] and SPLLCSR[SPLLCMRE] must be 1 and
RCM_SRIE[LOC], RCM_SRIE[LOL] must be 0). The only exception is during
standard clock switching, in which case the ‘clock switching sequence’ protocol must
be followed.
See note in section IO Signal Table.
26.1.3 System clock switching
For any clock switching of system clock, follow the below steps:
• Before doing a clock switch, configure all reset sources to be ‘Reset' (not as
Interrupt) via RCM_SRIE.
• Program each reset source as Interrupt via RCM_SRIE for a minimum delay time of
10 LPO.
• Execute the clock switch
• Wait/Poll for the clock switch to complete
• Configure every reset source back to original intended reset configuration (Interrupt
or Reset) via RCM_SRIE
NOTE
LOC flag would be raised when SOSC pulses are not detected
for 8 to 16 clock cycles of SIRC/256. Hence, the LOC
indication through reset to the system from the time when
oscillator is cut off will vary from 256 μs to 512 μs.
26.1.4 System clock and clock monitor requirement
1. System clock source SOSC/SPLL requirement: Ensure below sequence is
followed while switching system clock to SOSC/SPLL:
a. System clock source (SOSC/SPLL) is enabled
Chip-specific SCG information
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
530 NXP Semiconductors