NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1201 / 1761

The table below shows the delay that is added by the FTM channel input filter according
to its configuration.
Table 41-7. FTM Channel Input Filter Delay
FTM channel input filter FLTPS[3:0] bits Number of rising edges between the selected edge on
channel input and setting CHF bit
• channel does not have the input
filter, or
• channel input filter is disabled
(CHnFVAL[3:0] = 0)
FLTPS[3:0] = 0 • 3 rising edges of FTM input clock
FLTPS[3:0] ≠ 0 • 3 rising edges of FTM input clock, plus
• 1 rising edge of FTM filter clock
• channel has the input filter, and
• channel input filter is enabled
(CHnFVAL[3:0] ≠ 0)
FLTPS[3:0] = 0 • (4 + 4 × CHnFVAL[3:0]) rising edges of FTM input clock
FLTPS[3:0] ≠ 0 • 4 rising edges of FTM input clock, plus
• (1 + 4 × CHnFVAL[3:0]) rising edges of FTM filter clock
The following figures illustrate two examples of channel input filter.
FTM input clock
FTM counter
CnV register
CHF bit
Note:
PS[2:0] = 3'b000
channel (n) in input capture mode with capture only on rising edges
CHnFVAL[3:0] = 4'h2 (channel (n) input filter is enabled)
53
channel (n) input
54 55 56 57 58 59 60 61 62 63 64 65
(4 + 4 x CHnFVAL) = 12 rising edges of FTM input clock
64 xx
Figure 41-18. Example of Channel Input Filter when FLTPS[3:0] = 0
Chapter 41 FlexTimer Module (FTM)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1201