
On a power-on reset, the POR bit in the system reset register is set, indicating the user
should perform the WDOG fast test.
21.4.7.1 Testing each byte of the counter
The test procedure follows these steps:
1. Program the preferred watchdog timeout value in the TOVAL register during the
watchdog configuration time period.
2. Select a byte of the counter to test using the CS[TST] = 10b for the low byte;
CS[TST] = 11b for the high byte.
3. Wait for the watchdog to timeout. Optionally, in the idle loop, increment RAM
locations as a parallel software counter for later comparison. Because the RAM is not
affected by a watchdog reset, the timeout period of the watchdog counter can be
compared with the software counter to verify the timeout period has occurred as
expected.
4. The watchdog counter times out and forces a reset.
5. Confirm the WDOG flag in the system reset register is set, indicating that the
watchdog caused the reset. (The POR flag remains clear.)
6. Confirm that CS[TST] shows a test (10b or 11b) was performed.
If confirmed, the count and compare functions work for the selected byte. Repeat the
procedure, selecting the other byte in step 2.
NOTE
CS[TST] is cleared by a POR only and not affected by other
resets.
21.4.7.2 Entering user mode
After successfully testing the low and high bytes of the watchdog counter, the user can
configure CS[TST] to 01b to indicate the watchdog is ready for use in application user
mode. Thus if a reset occurs again, software can recognize the reset trigger as a real
watchdog reset caused by runaway or faulty application code.
As an ongoing test when using the default clock source, software can periodically read
the CNT register to ensure the counter is being incremented.
Chapter 21 Watchdog timer (WDOG)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors
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Summary of Contents for MWCT101 S Series
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Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
Page 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...
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Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
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Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
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Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
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