NXP Semiconductors MWCT101 S Series, Reference Manual

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• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse
width
• Independent FIFO structure for transmit and receive
• Separate configurable watermark for receive and transmit requests
• Option for receiver to assert request after a configurable number of idle
characters if receive FIFO is not empty
47.2.2 Modes of operation
47.2.2.1 Stop mode
The LPUART will remain functional during Stop mode, provided the CTRL[DOZEEN]
bit is clear and the asynchronous transmit and receive clock remain enabled. The
LPUART can generate an interrupt or DMA request to cause a wakeup from Stop mode.
If the LPUART is disabled in Stop mode, then it can generate a wakeup via the
STAT[RXEDGIF] flag if the receiver detects an active edge.
47.2.2.2 Debug mode
The LPUART remains functional in debug mode.
47.2.3 Signal Descriptions
Signal Description I/O
TXD Transmit data. This pin is normally an
output, but is an input (tristated) in single
wire mode whenever the transmitter is
disabled or transmit direction is
configured for receive data. I/O
RXD Receive data. I
CTS_B Clear to send. I
RTS_B Request to send. O
47.2.4 Block diagram
The following figure shows the transmitter portion of the LPUART.
Chapter 47 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1469