1. Switch to Round-Robin Channel Arbitration mode, change the channel priorities,
then switch back to Fixed Arbitration mode,
2. Disable all the channels, change the channel priorities, then enable the appropriate
channels.
16.6.7.2 Dynamic channel linking
Dynamic channel linking is the process of setting the
during channel execution (see the diagram in
TCD local memory at the end of channel execution, thus allowing the user to enable the
feature during channel execution.
Because the user is allowed to change the configuration during execution, a coherency
model is needed. Consider the scenario where the user attempts to execute a dynamic
channel link by enabling the TCDn_CSR[MAJORELINK] bit at the same time the
eDMA engine is retiring the channel. The TCDn_CSR[MAJORELINK] would be set in
the programmer’s model, but it would be unclear whether the actual link was made
before the channel retired.
The following coherency model is recommended when executing a dynamic channel link
request.
1. Write 1 to the TCDn_CSR[MAJORELINK] bit.
2. Read back the TCDn_CSR[MAJORELINK] bit.
3. Test the TCDn_CSR[MAJORELINK] request status:
• If TCDn_CSR[MAJORELINK] = 1, the dynamic link attempt was successful.
• If TCDn_CSR[MAJORELINK] = 0, the attempted dynamic link did not succeed
(the channel was already retiring).
For this request, the TCD local memory controller forces the
TCDn_CSR[MAJORELINK] bit to zero on any writes to a channel’s TCD.word7 after
that channel’s TCD.done bit is set, indicating the major loop is complete.
NOTE
bit before
writing the TCDn_CSR[MAJORELINK] bit. The
TCDn_CSR[DONE] bit is cleared automatically by the eDMA
engine after a channel begins execution.
Initialization/application information
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
368
NXP Semiconductors
Summary of Contents for MWCT101 S Series
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Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
Page 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...
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Page 430: ...Functional Description MWCT101xS Series Reference Manual Rev 3 07 2019 430 NXP Semiconductors...
Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
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Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
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Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
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