NXP Semiconductors MWCT101 S Series, Reference Manual

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49.3 FlexCAN signal descriptions
The FlexCAN module has two I/O signals connected to the external chip pins. These
signals are summarized in the following table and described in more detail in the next
subsections.
Table 49-4. FlexCAN signal descriptions
Signal Description I/O
CAN Rx CAN receive pin Input
CAN Tx CAN transmit pin Output
49.3.1 CAN Rx
This pin is the receive pin from the CAN bus transceiver. Dominant state is represented
by logic level 0. Recessive state is represented by logic level 1.
49.3.2 CAN Tx
This pin is the transmit pin to the CAN bus transceiver. Dominant state is represented by
logic level 0. Recessive state is represented by logic level 1.
49.4 Memory map/register definition
This section describes the registers and data structures in the FlexCAN module. The base
address of the module depends on the particular memory map of the chip.
49.4.1 FlexCAN memory mapping
The memory map for the FlexCAN module is shown in the following table.
The address space occupied by FlexCAN has 128 bytes for registers starting at the
module base address, followed by embedded RAM starting at address offset 0x0080.
FlexCAN signal descriptions
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1572 NXP Semiconductors