NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1399 / 1761

NOTE
About the Continuous Transfer bit (CONT) and Continuing
Command bit (CONTC):
• Continuous Transfer bit (CONT)=1 is used to keep PCS
asserted at end of frame, allowing the transfer to continue.
• Continuing Command bit (CONTC)=1 is used to indicate
that this command word should not terminate the existing
frame, and the transfer can continue using the new
command word.
The Continuing Command bit (CONTC)=1 is restricted in the
sense that the new command must load on a frame boundary,
and the only way for a transfer to continue from a frame
boundary, is when the previous command has the Continuous
Transfer bit (CONT)=1.
The current state of the existing command word can be read by reading the Transmit
Command Register (TCR). It requires at least 3 LPSPI functional clock cycles for the
transmit command register to update after the transmit command register is written
(assuming an empty FIFO) and the LPSPI must be enabled (Module Enable CR[MEN]
bit is set).
Writing the transmit command register does not initiate a SPI bus transfer, unless the
Transmit Data Mask (TCR[TXMSK]) bit is set. When the Transmit Data Mask bit is set,
a new command word will not be loaded until the end of the existing frame (based on
FRAMESZ configuration); at the end of the transfer, the TXMSK bit will be cleared.
In master mode, the LPSPI command word in the Transmit Command Register (TCR)
controls SPI attributes (using bits and fields in registers).
Table 45-8. LPSPI Command Word in Master Mode
Transmit Command Register
(TCR)
Description Can this bit/
field be
modified
during a
data
transfer?
Bit/Field Name
CPOL Clock Polarity Configures the polarity of the LPSPI_SCK pin. Any change of CPOL
value will cause a transition on the LPSPI_SCK pin. N
CPHA Clock Phase Configures the clock phase of the transfer. N
PRESCALE Prescaler Value Configures a prescaler used to divide the LPSPI functional clock, to
generate the timing parameters of the SPI bus transfer. Changing
PRESCALE in conjunction with PCS enables the LPSPI module to
connect to different slave devices at different frequencies. N
Table continues on the next page...
Chapter 45 Low Power Serial Peripheral Interface (LPSPI)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1399