NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 918 / 1761

Table 33-34. Word Program (Spansion Hyperflash/HyperRAM) (continued)
CADDR_DDR 0x3 0x10 16 bit column address
with lower 3 bits valid
rest 0(0005h),treated as
command
CMD_DDR 0x3 0x00 Write command with
wrapped burst type.
CMD_DDR 0x3 0xAA Write data to be sent to
flash as pre-command.
CMD_DDR Unlock Sequence 2
(second chip select
phase)
0x3 0x00 Write command with
wrapped burst type
CMD_DDR 0x3 0x00 8 bit address 00h
treated as command
CMD_DDR 0x3 0x00 8 bit address 00h
treated as command
CMD_DDR 0x3 0x55 8 bit address 55h
treated as command
CADDR_DDR 0x3 0x10 16 bit column address
with lower 3 bits valid
rest 0(0002h),treated as
command
CMD_DDR 0x3 0x00 Write command with
wrapped burst type
CMD_DDR 0x3 0x55 Write data to be sent to
flash as pre-command
CMD_DDR Program setup phase
(third chip select phase)
0x3 0x00 Write command with
wrapped burst type
CMD_DDR 0x3 0x00 8 bit address 00h
treated as command
CMD_DDR 0x3 0x00 8 bit address 00h
treated as command
CMD_DDR 0x3 0xAA 8 bit address AAh
treated as command
CADDR_DDR 0x3 0x10 16 bit column address
with lower 3 bits valid
rest 0(0005h),treated as
command
CMD_DDR 0x3 0x00 Write command with
wrapped burst type
CMD_DDR 0x3 0xA0 Write data to be sent to
flash as pre-command
CMD_DDR Command phase
(fourth/final chip select
phase)
0x3 0x00 Write command with
wrapped burst type
ADDR_DDR 0x3 0x18 24 bit row address
CADDR_DDR 0x3 0x10 16 bit column address
with lower 3 bits valid
rest 0
WRITE_DDR 0x3 0x2 2 bytes data written on
8 pads (D1D2)
Table continues on the next page...
Serial Flash Devices
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
918 NXP Semiconductors