NXP Semiconductors MWCT101 S Series, Reference Manual

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Table 7-3. Terms used
If you see this term... it also means this term...
Privileged Supervisor
Unprivileged or user User
7.2 Nested Vectored Interrupt Controller (NVIC)
Configuration
This section summarizes how the module has been configured in the chip. Full
documentation for this module is provided by Arm and can be found at
arm.com .
Nested Vectored
Interrupt Controller
(NVIC)
Arm
Cortex-M4+
core
Interrupts
Module
Module
Module
PPB
Figure 7-2. NVIC configuration
Table 7-4. Reference links to related information
Topic Related module Reference
Full description Nested Vectored
Interrupt Controller
(NVIC)
Arm Cortex-M4F Technical Reference Manual - Nested Vectored Interrupt
Controller
System memory map — Refer to the MWCT101xS_memory_map.xlsx attached to this document.
Clocking — Clock distribution
Power management — Power management
Private Peripheral Bus
(PPB)
Arm Cortex-M4 core Arm Cortex-M4F Technical Reference Manual - Private Peripheral Bus
(PPB)
7.2.1 Interrupt priority levels
This device supports 16 priority levels for interrupts. Therefore, in the NVIC each source
in the IPR registers contains 4 bits. For example, the IPR0 diagram is shown below.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQ3
0 0 0 0
IRQ2
0 0 0 0
IRQ1
0 0 0 0
IRQ0
0 0 0 0
W
Nested Vectored Interrupt Controller (NVIC) Configuration
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
100 NXP Semiconductors