NXP Semiconductors MWCT101 S Series, Reference Manual

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NOTE
See Arm documentation for more details on WFI instructions.
Table 34-1. Chip power modes
Chip mode Description Core mode Normal
recovery
method
Normal Run Default mode out of reset; on-chip voltage regulator is on. Run -
High Speed Run
(HSRUN)
Allows maximum performance of the chip. In this mode, the chip can
operate at a higher frequency as compared to Normal Run mode but
with restricted functionalities.See
Module operation in available power
modes for more details. See Internal clocking requirements for more
details.
Run -
Normal Stop (via
WFI instruction)
Places the chip in static state. In this power mode, all registers are
retained and LVD protection is maintained.
• NVIC is disabled.
• AWIC is used to wake up from interrupt.
• Some peripheral clocks are stopped.
See Module operation in available power modes for more details.
Sleep Deep Interrupt
Very Low Power
Run (VLPR)
On-chip voltage regulator is in a low power mode that supplies only
enough power to run the chip at a reduced frequency.
• Reduced-frequency flash memory access mode (1 MHz)
• LVD off
• SIRC provides a low power 4 MHz source for the core, the bus,
and the peripheral clocks
Run -
Very Low Power
Stop (VLPS, via
WFI instruction)
Places the chip in a static state with Low Voltage Detect (LVD)
operation off. This is the lowest-power mode in which the pin interrupts
are functional.
• Some peripheral clocks are stopped. See Module operation in
available power modes .
• The LPTMR, RTC, and CMP can be used.
• The NVIC is disabled.
• The AWIC is used to wake from interrupt.
• The on-chip voltage regulator is in a low power mode that
supplies only the power needed to run the chip at a reduced
frequency.
• All SRAM is operational (content is retained and I/O states are
maintained).
Sleep Deep Interrupt
NOTE
Before disabling a module, its interrupts and DMA requests
should be disabled.
34.3 Entering and exiting power modes
The WFI instruction invokes stop modes for the chip. The processor exits the low-power
mode via an interrupt. See
Nested Vectored Interrupt Controller (NVIC) Configuration
for a description of interrupt operation and which peripherals can cause interrupts.
Entering and exiting power modes
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
930 NXP Semiconductors