NXP Semiconductors MWCT101 S Series, Reference Manual, Page: 936 / 1761

34.6 Shutdown sequencing for power modes
When entering stop or other low-power mode, clocks are shut off in an orderly sequence
to safely place the chip in the targeted low-power state. All low-power entry sequences
are initiated by the core executing a WFI instruction. The Arm core's outputs,
SLEEPDEEP and SLEEPING, trigger entry to the various low-power modes:
• Low power modes equate to: SLEEPING & SLEEPDEEP
When entering low power modes, the chip performs the following sequence:
Table 34-2. Low power entry sequence
Step Action
1 The chip immediately shuts off core and system clocks to the Arm Cortex-M4 core.
2 The chip polls the stop-acknowledge indications from the non-core crossbar masters (DMA), supporting
peripherals (SPI, PIT), and the flash memory controller for indications that system clocks, bus clock, and/or
flash memory clock need to be left enabled to complete a previously initiated operation, effectively stalling
entry to the targeted low power mode. When all acknowledges are detected, system clock, bus clock and
flash memory clock are turned off simultaneously.
3 The SCG and Mode Controller shut off clock sources and/or the internal supplies driven from the internal
regulator as defined for the targeted low power mode.
The debugger modules support transitions from Stop, VLPS back to a halted state when
the debugger is enabled. This transition is initiated by setting the Debug Request field in
the MDM-AP control register. As part of this transition, system clocking is reestablished
and is equivalent to Normal Run/VLPR mode clocking configuration.
34.7 Power mode restrictions on flash memory programming
The flash memory should not be programmed or erased while the chip is operating in:
• VLPR mode
• HSRUN mode
No FTFC commands of any type, including CSE commands (for CSEc parts), are
available when the chip is in these modes.
34.8 Module operation in available power modes
Table 34-4 illustrates module functionality in each of the available modes.
Shutdown sequencing for power modes
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
936 NXP Semiconductors