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In Modified Combine PWM mode, the channel (n+1) ELSB:ELSA bits are not used in
the generation of the channels (n) and (n+1) output. However, if channel (n) ELSB:ELSA
= 0:0, then the channel (n) output is not controlled by FTM, and if channel (n+1)
ELSB:ELSA = 0:0, then the channel (n+1) output is not controlled by FTM.
FTM counter
channel (n) match
channel (n) output
with ELSB:ELSA = 1:0
with ELSB:ELSA = X:1
channel (n) output
channel (n+1) match
Figure 41-47. Modified Combine PWM Mode
The Modified Combine PWM mode allows the offset addition of the duty cyle, thus, in
some cases, the C(n+1)V match can happen on the next FTM counter period. For CNTIN
≥ 0, MOD > 0, and CNTIN < MOD, this situation happens when C(n)V > C(n+1)V.
FTM counter
C(n)V match
(C(n)V is fixed)
channel (n) output
with ELSB:ELSA = 1:0
C(n+1)V is updated
with its write buffer
C(n+1)V match
0% duty cycle
Figure 41-48. Modified Combine PWM Mode Examples
If more than one pair of channels are configured in Modified Combine PWM Mode, it is
possible to fix an offset for the channel (n) match edge of each pair with respect to other
pairs. This behavior is useful in the generation of lighting PWM control signals where it
is desirable that edges are not coincident with each other pair to help eliminate noise
generation. The C(n)V register value is the shift of the PWM pulse with respect to the
beginning of FTM counter period (FTM counter = CNTIN).
Functional Description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1218
NXP Semiconductors
Summary of Contents for MWCT101 S Series
Page 2: ...MWCT101xS Series Reference Manual Rev 3 07 2019 2 NXP Semiconductors...
Page 42: ...MWCT101xS Series Reference Manual Rev 3 07 2019 42 NXP Semiconductors...
Page 50: ...Conventions MWCT101xS Series Reference Manual Rev 3 07 2019 50 NXP Semiconductors...
Page 70: ...Aliased bit band regions MWCT101xS Series Reference Manual Rev 3 07 2019 70 NXP Semiconductors...
Page 78: ...Pinout diagrams MWCT101xS Series Reference Manual Rev 3 07 2019 78 NXP Semiconductors...
Page 96: ...WCT101xS safety concept MWCT101xS Series Reference Manual Rev 3 07 2019 96 NXP Semiconductors...
Page 130: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 130 NXP Semiconductors...
Page 284: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 284 NXP Semiconductors...
Page 430: ...Functional Description MWCT101xS Series Reference Manual Rev 3 07 2019 430 NXP Semiconductors...
Page 472: ...Application Information MWCT101xS Series Reference Manual Rev 3 07 2019 472 NXP Semiconductors...
Page 528: ...Module clocks MWCT101xS Series Reference Manual Rev 3 07 2019 528 NXP Semiconductors...
Page 634: ...SRAM configuration MWCT101xS Series Reference Manual Rev 3 07 2019 634 NXP Semiconductors...
Page 818: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 818 NXP Semiconductors...
Page 960: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 960 NXP Semiconductors...
Page 992: ...ADC calibration scheme MWCT101xS Series Reference Manual Rev 3 07 2019 992 NXP Semiconductors...
Page 1348: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 1348 NXP Semiconductors...
Page 1366: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 1366 NXP Semiconductors...
Page 1514: ...Functional description MWCT101xS Series Reference Manual Rev 3 07 2019 1514 NXP Semiconductors...
Page 1726: ...Debug and security MWCT101xS Series Reference Manual Rev 3 07 2019 1726 NXP Semiconductors...
Page 1760: ...MWCT101xS Series Reference Manual Rev 3 07 2019 1760 NXP Semiconductors...