NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1604 / 1761

Field Function
Considering that the Rx FIFO occupies the memory space originally reserved for MB0-5, RFFN
should be programmed with a value corresponding to a number of filters not greater than the
number of available memory words, which can be calculated as follows:
(SETUP_MB - 6) × 4
where SETUP_MB is the smaller of the parameter NUMBER_OF_MB and MCR[MAXMB].
The number of remaining mailboxes available will be:
(SETUP_MB - 8) - (RFFN × 2)
If the number of Rx FIFO filters programmed through RFFN exceeds the SETUP_MB value
(memory space available), then the exceeding ones will not be functional.
NOTE: • The number of the last remaining available mailboxes is defined by the smaller of
NUMBER_OF_MB minus 1 and MCR[MAXMB].
• If Rx Individual Mask registers are not enabled then all Rx FIFO filters are affected by the
Rx FIFO Global Mask.
23-19
TASD
Tx Arbitration Start Delay
This 5-bit field indicates how many CAN bits the Tx arbitration process start point can be delayed from
the first bit of CRC field on CAN bus. See
Tx arbitration start delay for more details. This field can be
written only in Freeze mode because it is blocked by hardware in other modes.
18
MRP
Mailboxes Reception Priority
If this bit is set the matching process starts from the mailboxes and if no match occurs the matching
continues on the Rx FIFO. This bit can be written only in Freeze mode because it is blocked by hardware
in other modes.
0b - Matching starts from Rx FIFO or Enhanced Rx FIFO and continues on mailboxes.
1b - Matching starts from mailboxes and continues on Rx FIFO.
17
RRS
Remote Request Storing
If this bit is asserted a remote request frame is submitted to a matching process and stored in the
corresponding message buffer in the same fashion as a data frame. No automatic remote response
frame will be generated.
If this bit is negated the remote request frame is submitted to a matching process and an automatic
remote response frame is generated if a message buffer with CODE=0b1010 is found with the same ID.
This bit can be written only in Freeze mode because it is blocked by hardware in other modes.
0b - Remote response frame is generated.
1b - Remote request frame is stored.
16
EACEN
Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
This bit controls the comparison of IDE and RTR bits within Rx mailbox filters with their corresponding
bits in the incoming frame by the matching process. This bit does not affect matching for Rx FIFO. This
bit can be written only in Freeze mode because it is blocked by hardware in other modes.
0b - Rx mailbox filter’s IDE bit is always compared and RTR is never compared despite mask bits.
1b - Enables the comparison of both Rx mailbox filter’s IDE and RTR bit with their corresponding
bits within the incoming frame. Mask bits do apply.
15
TIMER_SRC
Timer Source
Selects the time tick source used for incrementing the free running timer counter. This bit can be written
in Freeze mode only.
NOTE: This field is not supported in every instance. The following table includes only supported
registers.
Table continues on the next page...
Memory map/register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1604 NXP Semiconductors