NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1758 / 1761

LPUART changes
A.48.1 Chip-specific LPUART information changes
• Updated Instantiation Information
A.48.2 LPUART module changes
• In the section Register definition , added the note "Writing a Read-Only (RO) register or reading a Write-Only (WO)
register can cause bus errors. This module will not check if programmed values in the registers are correct; the
application software must ensure that valid programmed values are being written"
• Clarified operation of data match wakeup
• Minor editorial updates
• Added
Clocking and Resets
• Removed "In the case of a framing error, provided the received character ... " from Data sampling technique
• Added description to the Parameter Register (PARAM)
FlexIO changes
A.49.1 Chip-specific FlexIO changes
• No substantial content changes
A.49.2 FLEXIO module changes
• In SPI Slave : :Minor correction for TIMCFGn register in table 'SPI Slave (CPHA=0) Configuration'
• Removed STOP mode related content
• Minor update in Features section
FlexCAN changes
A.50.1 Chip-specific FlexCAN information changes
• No substantial content changes
A.48
A.49
A.50
LPUART changes
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1758 NXP Semiconductors