NXP Semiconductors MWCT101 S Series, Reference Manual

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Field Function
10-8
TXCOUNT
Transmit Counter
The value in this register indicates the number of datawords that are in the transmit FIFO/buffer. If a
dataword is being transmitted, that is, in the transmit shift register, it is not included in the count. This
value may be used in conjunction with FIFO[TXFIFOSIZE] to calculate how much room is left in the
transmit FIFO/buffer.
7-2
—
Reserved
1-0
TXWATER
Transmit Watermark
When the number of datawords in the transmit FIFO/buffer is equal to or less than the value in this
register field, an interrupt or a DMA request is generated. For proper operation, the value in TXWATER
must be set to be less than the size of the transmit buffer/FIFO size as indicated by FIFO[TXFIFOSIZE]
and FIFO[TXFE].
47.4 Functional description
The LPUART supports full-duplex, asynchronous, NRZ serial communication and
comprises a baud rate generator, transmitter, and receiver block. The transmitter and
receiver operate independently, although they use the same baud rate generator. The
following describes each of the blocks of the LPUART.
47.4.1 Clocking and Resets
Table 47-2. Clocks
LPUART Functional
clock The LPUART functional clock is asynchronous to the bus clock and can remain enabled in low
power modes to support transmit and/or receive, including low power wakeups.
Bus clock The bus clock is only used for bus accesses to the control and configuration registers. The bus
clock frequency must be sufficient to support the data bandwidth requirements of the LPUART
transmit and receive registers, including the FIFOs.
Table 47-3. Resets
Chip reset The logic and registers for the LPUART transmitter and receiver are reset to their default state on a
chip reset.
Software reset Resets the LPUART logic and registers to their default state, except for the Global Register. The
LPUART software reset is in the Global Register GLOBAL[RST].
FIFO reset The LPUART implements write-only control bits that reset the transmit FIFO (FIFO[TXFLUSH]) and
receive FIFO (FIFO[RXFLUSH]). After a FIFO is reset, that FIFO is empty.
Chapter 47 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1497