NXP Semiconductors MWCT101 S Series, Reference Manual

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Field Function
—
9
CLKO
Clock Output
0b - The 32 kHz clock is output to other peripherals.
1b - The 32 kHz clock is not output to other peripherals.
8
—
Reserved
7
LPOS
LPO Select
When set, the RTC prescaler increments using the LPO 1 kHz clock and not the RTC 32.768 kHz clock.
The LPO increments the prescaler from bit TPR[5] (TPR[4:0] are ignored), supporting close to 1 second
increment of the seconds register. Although compensation is supported when clocked from the LPO,
TCR[4:0] of the compensation register are also ignored and only TCR[7:5] set the compensation value
(can overflow after 1020 to 1027 cycles).
0b - RTC prescaler increments using 32.768 kHz clock.
1b - RTC prescaler increments using 1 kHz LPO, bits [4:0] of the prescaler are ignored.
6
—
Reserved
5
CPS
Clock Pin Select
0b - The prescaler output clock (as configured by TSIC) is output on RTC_CLKOUT.
1b - The RTC 32.768 kHz clock is output on RTC_CLKOUT, provided it is output to other
peripherals.
4
—
Reserved
3
UM
Update Mode
Allows SR[TCE] to be written even when the Status Register is locked. When set, the SR[TCE] can be
written if the SR[TIF] or SR[TOF] are set or if the SR[TCE] is clear. Whenever both SR[TCE] and CR[UM]
are set, then SR[TCE] should only be written once either SR[TIF] or SR[TOF] are set.
0b - Registers cannot be written when locked.
1b - Registers can be written when locked under limited conditions.
2
SUP
Supervisor Access
0b - Non-supervisor mode write accesses are not supported and generate a bus error.
1b - Non-supervisor mode write accesses are supported.
1
—
Reserved
0
SWR
Software Reset
0b - No effect.
1b - Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by
software explicitly clearing it.
44.3.1.7 RTC Status Register (SR)
44.3.1.7.1 Offset
Register Offset
SR 14h
Chapter 44 Real Time Clock (RTC)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1357