NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 298 / 1761

16.2.1 eDMA system block diagram
Figure 16-1 illustrates the components of the eDMA system, including the eDMA
module ("engine").
1
Transfer Control
Descriptor (TCD)
eDMA engine
Data Path
eDMA system
0
Program Model/
64
Control
n-1
To/F
rom Cr
ossbar S
witch
2
Channel Arbitration
Address Path
Read Data
Write Data
Address
Read Data
Write Data
Write Address
Int
er
nal P
er
ipher
al Bus
eDMA Peripheral
Request
eDMA Done
Figure 16-1. eDMA system block diagram
16.2.2 Block parts
The eDMA module is partitioned into two major modules: the eDMA engine and the
transfer-control descriptor local memory.
The eDMA engine is further partitioned into four submodules:
Table 16-2. eDMA engine submodules
Submodule Function
Address path This block implements registered versions of two channel transfer control descriptors, channel x
and channel y, and manages all master bus-address calculations. All the channels provide the
same functionality. This structure allows data transfers associated with one channel to be
Table continues on the next page...
Introduction
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
298 NXP Semiconductors