NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1678 / 1761

(0b0000) or EMPTY
1
(0b0100). Also, Tx MBs cannot be
locked.
Suppose, for example, that the FIFO is disabled and the second and the fifth MBs of the
array are programmed with the same ID, and FlexCAN has already received and stored
messages into these two MBs. Suppose now that the CPU decides to read MB number 5
and at the same time another message with the same ID is arriving. When the CPU reads
the Control and Status word of MB number 5, this MB is locked. The new message
arrives and the matching algorithm finds out that there are no free-to-receive MBs, so it
decides to override MB number 5. However, this MB is locked, so the new message
cannot be written there. It will remain in the Rx SMB waiting for the MB to be unlocked,
and only then will be written to the MB.
If the MB is not unlocked in time and yet another new message with the same ID arrives,
then the new message overwrites the one on the Rx SMB and there will be no indication
of lost messages either in the CODE field of the MB or in the Error and Status Register.
While the message is being moved in from the Rx SMB to the MB, the BUSY bit on the
CODE field is asserted. If the CPU reads the Control and Status word and finds out that
the BUSY bit is set, it should defer accessing the MB until the BUSY bit is negated.
Note
If the BUSY bit is asserted or if the MB is empty, then reading
the Control and Status word does not lock the MB.
Inactivation takes precedence over locking. If the CPU inactivates a locked Rx MB, then
its lock status is negated and the MB is marked as invalid for the current matching round.
Any pending message on the Rx SMB will not be transferred anymore to the MB. An
MB is unlocked when the CPU reads the Free Running Timer Register (see
Free Running
Timer (TIMER) ), or the C/S word of another MB.
Lock and unlock mechanisms have the same functionality in both Normal and Freeze
modes.
An unlock during Normal or Freeze mode results in the move-in of the pending message.
However, the move-in is postponed if an unlock occurs during a low power mode (see
Modes of operation ), and it takes place only when the module returns to Normal or
Freeze modes.
1. In previous FlexCAN versions, reading the C/S word locked the MB even if it was
EMPTY. This behavior is maintained when the IRMQ bit is negated.
Functional description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1678 NXP Semiconductors