NXP Semiconductors MWCT101 S Series, Reference Manual

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Field Function
0b - Timer sync feature disabled
1b - Timer sync feature enabled
4
LBUF
Lowest Buffer Transmitted First
This bit defines the ordering mechanism for message buffer transmission. When asserted,
MCR[LPRIOEN] does not affect the priority arbitration. This bit can be written in Freeze mode only,
because it is blocked by hardware in other modes.
0b - Buffer with highest priority is transmitted first.
1b - Lowest number buffer is transmitted first.
3
LOM
Listen-Only Mode
This bit configures FlexCAN to operate in Listen-Only mode. In this mode, transmission is disabled, all
error counters described in the ECR register are frozen, and the module operates in a CAN Error Passive
mode. Only messages acknowledged by another CAN station will be received. If FlexCAN detects a
message that has not been acknowledged, it will flag a BIT0 error without changing the receive error
counter (ECR[RXERRCNT]), as if it was trying to acknowledge the message.
Listen-Only mode is acknowledged by the state of ESR1[FLTCONF] indicating Passive Error. There can
be some delay between the Listen-Only mode request and acknowledge.
This bit can be written in Freeze mode only because it is blocked by hardware in other modes.
0b - Listen-Only mode is deactivated.
1b - FlexCAN module operates in Listen-Only mode.
2-0
PROPSEG
Propagation Segment
This 3-bit field defines the length of the propagation segment in the bit time. The valid programmable
values are 0–7. This field can be written only in Freeze mode because it is blocked by hardware in other
modes.
Propagation segment time = (P 1) × time-quanta.
Time-quantum = one Sclock period.
49.4.2.4 Free Running Timer (TIMER)
49.4.2.4.1 Offset
Register Offset
TIMER 8h
49.4.2.4.2 Function
This register represents a 16-bit free-running counter that can be read and written by the
CPU. The timer starts from 0x0 after Reset, counts linearly to 0xFFFF, and wraps around.
When CTRL2[TIMER_SRC] is asserted, the timer is continuously incremented by an
external time tick. The time tick must be synchronous to the peripheral clock, with a
minimum pulse width of one clock cycle.
Memory map/register definition
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1584 NXP Semiconductors