NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1573 / 1761

Each individual register is identified by its complete name and the corresponding
mnemonic . The access type can be Supervisor (S) or Unrestricted (U) . Most of the
registers can be configured to have either Supervisor or Unrestricted access by
programming MCR[SUPV] . These registers are identified as S/U in the Access column
of
Table 49-5 .
NOTE
An invalid register access will result in a bus error. This
includes reading a write-only register, writing a read-only
register, or accessing an invalid address.
Table 49-5. Register access and reset information
Register Access type
Affected by
hard reset
Affected by
soft reset
Module Configuration Register (MCR) S Yes Yes
Control 1 register (CTRL1) S/U Yes No
Free Running Timer register (TIMER) S/U Yes Yes
Rx Mailboxes Global Mask register (RXMGMASK) S/U No No
Rx Buffer 14 Mask register (RX14MASK) S/U No No
Rx Buffer 15 Mask register (RX15MASK) S/U No No
Error Counter Register (ECR) S/U Yes Yes
Error and Status 1 Register (ESR1) S/U Yes Yes
Interrupt Masks 1 register (IMASK1) S/U Yes Yes
Interrupt Flags 1 register (IFLAG1) S/U Yes Yes
Control 2 Register (CTRL2) S/U Yes No
Error and Status 2 Register (ESR2) S/U Yes Yes
CRC Register (CRCR) S/U Yes Yes
Rx FIFO Global Mask register (RXFGMASK) S/U No No
Rx FIFO Information Register (RXFIR) S/U No No
CAN Bit Timing Register (CBT) S/U Yes No
Message buffers S/U No No
Rx Individual Mask Registers S/U No No
Pretended Networking Control 1 register (CTRL1_PN) S/U Yes Yes
Pretended Networking Control 2 register (CTRL2_PN) S/U Yes Yes
Pretended Networking Wake Up Match register (WU_MTC) S/U Yes Yes
Pretended Networking ID Filter 1 Register (FLT_ID1) S/U Yes Yes
Pretended Networking DLC Filter register (FLT_DLC) S/U Yes Yes
Pretended Networking Payload Low Filter 1 register (PL1_LO) S/U Yes Yes
Pretended Networking Payload High Filter 1 register (PL1_HI) S/U Yes Yes
Pretended Networking ID Filter 2 Register / ID Mask register
(FLT_ID2_IDMASK)
S/U Yes Yes
Pretended Networking Payload Low Filter 2 Register / Payload Low Mask
Register (PL2_PLMASK_LO)
S/U Yes Yes
Table continues on the next page...
Chapter 49 FlexCAN
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1573