NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 967 / 1761

36.6.1.4.1 Offset
Register Offset
REGSC 2h
36.6.1.4.2 Function
This register contains general control and status bits for the regulator and the LPO.
36.6.1.4.3 Diagram
Bits 7 6 5 4 3 2 1 0
R
LPODIS
LPOSTAT
0
REGFP M
CLKBIASDIS
BIASE N
W
Reset
0
1
u 0 0 0 1 0 0
1. Cleared on power on reset, unaffected by other reset.
36.6.1.4.4 Fields
Field Function
7
LPODIS
LPO Disable Bit
This bit enables or disable the low power oscillator.
NOTE: After disabling the LPO a time of 2 LPO clock cycles is required before it is allowed to enable it
again. Violating this waiting time of 2 cycles can result in malfunction of the LPO.
0b - Low power oscillator enabled
1b - Low power oscillator disabled
6
LPOSTAT
LPO Status Bit
This bit shows the status of the LPO clock to be either in high phase (logic 1) or low phase (logic 0) of the
clock period. Software can poll this status bit to measure actual LPO clock frequency and eventually use
the LPOTRIM[4:0] register to change the LPO frequency.
0b - Low power oscillator in low phase
1b - Low power oscillator in high phase
5-3
—
Reserved
2
REGFPM
Regulator in Full Performance Mode Status Bit
This read-only bit provides the current status of the internal voltage regulator.
0b - Regulator is in low power mode or transition to/from
1b - Regulator is in full performance mode
1
CLKBIASDIS
Clock Bias Disable Bit
Table continues on the next page...
Chapter 36 Power Management Controller (PMC)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 967