NXP Semiconductors MWCT101 S Series, Reference Manual

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Field Function
27
FRMERR_FAST
Form Error in the Data Phase of CAN FD frames with the BRS bit set
This bit indicates that a form error has been detected by the receiver node in the data phase of CAN FD
frames with the BRS bit set, that is, a fixed-form bit field contains at least one illegal bit.
0b - No such occurrence.
1b - A form error occurred since last read of this register.
26
STFERR_FAST
Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
This bit indicates that a stuffing error has been detected in the data phase of CAN FD frames with the
BRS bit set.
0b - No such occurrence.
1b - A stuffing error occurred since last read of this register.
25-22
—
Reserved
21
ERROVR
Error Overrun
This bit indicates that an error condition occurred when any error flag is already set. This bit is cleared by
writing it to 1.
0b - Overrun has not occurred.
1b - Overrun has occurred.
20
ERRINT_FAST
Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
This bit indicates that at least one of the error bits detected in the data phase of CAN FD frames with the
BRS bit set (BIT1ERR_FAST, BIT0ERR_FAST, CRCERR_FAST, FRMERR_FAST, or STFERR_FAST)
is set. If the corresponding mask bit CTRL2[ERRMSK_FAST] is set, an interrupt is generated to the CPU.
This bit is cleared by writing it to 1. Writing 0 has no effect.
0b - No such occurrence.
1b - Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit
set.
19
BOFFDONEINT
Bus Off Done Interrupt
This bit is set when the Tx Error Counter (TXERRCNT) has finished counting 128 occurrences of 11
consecutive recessive bits on the CAN bus and is ready to leave Bus Off. If the corresponding mask bit in
the Control 2 Register (BOFFDONEMSK) is set, an interrupt is generated to the CPU. This bit is cleared
by writing it to 1. Writing 0 has no effect.
0b - No such occurrence.
1b - FlexCAN module has completed Bus Off process.
18
SYNCH
CAN Synchronization Status
This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate
in the communication process. It is set and cleared by the FlexCAN. See the table in the overall ESR1
register description.
0b - FlexCAN is not synchronized to the CAN bus.
1b - FlexCAN is synchronized to the CAN bus.
17
TWRNINT
Tx Warning Interrupt Flag
If MCR[WRNEN] is asserted, TWRNINT is set when the TXWRN flag transitions from 0 to 1, meaning
that the Tx error counter reached 96. If the corresponding mask bit in the Control 1 Register
(CTRL1[TWRNMSK]) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1.
When WRNEN is negated, this flag is masked. CPU must clear this flag before disabling the bit.
Otherwise it will be set when WRNEN is set again. Writing 0 has no effect. This flag is not generated
during Bus Off state. This bit is not updated during Freeze mode.
When FlexCAN returns to Normal mode from Pretended Network mode (see Receive process under
Pretended Networking mode ), this bit is not updated.
0b - No such occurrence.
1b - The Tx error counter transitioned from less than 96 to greater than or equal to 96.
Table continues on the next page...
Chapter 49 FlexCAN
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 1595