NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 1312 / 1761

Field Function
0b - No Action
1b - Clear the Timer Enable bit (TCTRL1[T_EN]) for Timer Channel 1
0
CLR_T_EN_0
Clear Timer 0 Enable
• To disable timer channel 0, write '1' to Clear Timer 0 Enable bit.
• The Clear Timer 0 Enable bit can be used in addition to Timer Enable bit (T_EN) in TCTRL0
register.
• Writing a 1 to Clear Timer 0 Enable bit will not enable the counter.
• The Clear Timer 0 Enable bit is self-clearing, which means that the Clear Timer 0 Enable bit will
always read 0.
0b - No action
1b - Clear the Timer Enable bit (TCTRL0[T_EN]) for Timer Channel 0
42.4.1.9 Timer Value Register (TVAL0 - TVAL3)
42.4.1.9.1 Offset
Register Offset
TVAL0 20h
TVAL1 30h
TVAL2 40h
TVAL3 50h
42.4.1.9.2 Function
• In compare modes: the Timer Value Registers (TVALn) select the timeout period for
the timer channels.
• In capture modes: the Timer Value Registers (TVALn) are loaded with the value of
the counter when the trigger asserts.
NOTE
Unless the Module Clock Enable bit (MCR[M_CEN]) is set
(=1, peripheral clock to timers is enabled), then reading or
writing the TVALn register will generate a transfer error.
Memory Map and Registers
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
1312 NXP Semiconductors