NXP Semiconductors MWCT101 S Series, Reference Manual

Page: 888 / 1761

Table 33-14. Instruction set (continued)
Instruction
Instruction
encoding
Pins Operand Action on Serial Flash(es)
of column
address is to
be sent)
incoming address in case of AHB and the value of
QSPI_SFAR in case of IP. This will be appended with zero if
CAS is less than number of pads for a Flash.
STOP 8'd0 NA NA Stop execution; deassert CS
1. For a one pad instruction, MODE2 will take 2 serial flash clock cycles on the flash interface.
2. For a one pad instruction, MODE4 will take 4 serial flash clock cycles on the flash interface. For a 4 pad instruction,
MODE4 will take 1 serial flash clock cycle on the flash interface.
3. For a one pad instruction, MODE2_DDR will take 1 serial flash clock cycle on the flash interface.
4. For a one pad instruction, MODE4_DDR will take 2 serial flash clock cycles on the flash interface. For a 4 pad instruction
MODE4_DDR will take half a cycle on the serial flash interface.
The programmable sequence engine allows the user to configure the QuadSPI module
according to the serial flash connected on board. The flexible structure is easily adaptable
to new command/protocol changes from different vendors.
33.7.2.2 Flexible AHB buffers
In order to reduce the latency of the reads for AHB masters, the data read from the serial
flash is buffered in flexible AHB buffers. There are four such flexible buffers. The size of
each of these buffers is configurable with the minimum size being 0 Bytes and maximum
size being the size of the complete buffer instantiated.The size of buffer 0 is defined as
being from 0 to QSPI_BUF0IND. The Size of buffer 1 is from QSPI_BUF0IND to
QSPI_BUF1IND, buffer2 is from QSPI_BUF1IND to QSPI_BUF2IND and buffer 3 is
from QSPI_BUF2IND to the size of the complete buffer, which is given in the chip-
specific QuadSPI information.
Each flexible AHB buffer is associated with the following
1. An AHB master. Optionally, buffer3 may be configured as an "all master" buffer by
setting the QSPI_BUF3CR[ALLMST] bit. When buffer3 is configured in such a
way, any access from a master not associated with any other buffer is routed to
buffer3.
2. A datasize field representing the amount of data to be fetched from the flash on every
"missed" access.
The master port number of every incoming request is checked and the data is returned/
fetched into the corresponding associated buffer. Every "missed" access to the buffer
causes the controller to clear the buffer and fetch QSPI_BUFxCR[ADATSZ] amount of
data from the serial flash.As such, there is no benefit in configuring a buffer size of
greater than ADATSZ, as the locations greater than ADATSZ will never be used. For any
Functional Description
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
888 NXP Semiconductors