NXP Semiconductors MWCT101 S Series, Reference Manual

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Field Function
1b - The last recorded error was a configuration error detected in the TCDn_DADDR field.
TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
4
DOE
Destination Offset Error
0b - No destination offset configuration error
1b - The last recorded error was a configuration error detected in the TCDn_DOFF field.
TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
3
NCE
NBYTES/CITER Configuration Error
0b - No NBYTES/CITER configuration error
1b - The last recorded error was a configuration error detected in the TCDn_NBYTES or
TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and
TCDn_ATTR[DSIZE], orTCDn_CITER[CITER] is equal to zero, orTCDn_CITER[ELINK] is not equal
to TCDn_BITER[ELINK]
2
SGE
Scatter/Gather Configuration Error
0b - No scatter/gather configuration error
1b - The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This
field is checked at the beginning of a scatter/gather operation after major loop completion if
TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
1
SBE
Source Bus Error
0b - No source bus error
1b - The last recorded error was a bus error on a source read
0
DBE
Destination Bus Error
0b - No destination bus error
1b - The last recorded error was a bus error on a destination write
16.4.5.4 Enable Request Register (ERQ)
16.4.5.4.1 Offset
Register Offset
ERQ Ch
16.4.5.4.2 Function
The ERQ register provides a bit map for the 16 channels to enable the request signal for
each channel. The state of any given channel enable is directly affected by writes to this
register; it is also affected by writes to the SERQ and CERQ registers. These registers are
provided so the request enable for a single channel can easily be modified without
needing to perform a read-modify-write sequence to this register.
DMA request input signals and this enable request flag must be asserted before a
channel's hardware service request is accepted. The state of the DMA enable request flag
does not affect a channel service request made explicitly through software or a linked
channel request.
Chapter 16 Enhanced Direct Memory Access (eDMA)
MWCT101xS Series Reference Manual, Rev. 3, 07/2019
NXP Semiconductors 309